Power Management (3)：PCIe ASPM

In addition to CPU power saving features, PCIe defines an important power saving feature for PCIe devices.

In this blog, three topics will be covered:

1. What is ASPM?
2. How do we know whether ASPM is enabled?
3. Who controls ASPM?

Please refer to PCIe specification and ACPI specification for complete definition.

Active State Power Management：

ASPM (Active State Power Management) is a power-saving protocol defined in PCI-Express Specification.

Two low power states are defined in PCIe: L0s and L1 as below:

"The L0s low power Link state is optimized for short entry and exit latencies, while providing substantial power savings."

"The L1 Link state is optimized for maximum power savings at a cost of longer entry and exit latencies."

L0s and L1 can be enabled and disabled independently; however, whether L0s and L1 can be enabled depends on the latency of PCIe devices and root ports. Software must enable L0s and L1 with cautions.

ASPM Registers in PCI(E) Configuration Space：

L0s and L1 are enabled by writing to the registers in PCI(e) configuration space. PCI Express capability has an ID of 0x10. The register 0x40 in Figure 1 and the register 0xD0 in Figure 2 are the examples of PCI Express capability.

Figure 1 - PCIe Root Port

Bit [11..10] of the Link Capabilities Reigster (Offset 0x0C of PCI Express capability) reports ASPM supports. Root Port in Figure 1 and Device in Figure 2 report supports for both L0s and L1.

Similarly, Bit [11..10] of the Link Control Register (Offset 0x10 of PCI Express capability) reports ASPM enables. Root Port in Figure 1 and Device in Figure 2 report both L0s and L1 are enabled.

Figure 2 - PCIe Device

It should be noted that L0s and L1 must be enabled on both ends, i.e. the root port and the device, in order for ASPM to work, as shown in the example of Figure 1 (root port) and Figure 2 (device).

ASPM Control by Software：

ASPM is a hardware feature, but it is enabled by "software". The question is which software is in charge of enabling ASPM.

Answer: Both BIOS and Operating System can control ASPM, and the flow is as below:

1. BIOS sets ASPM settings during POST, and hands control to OS
2. OS initializes and sets ASPM settings.

It is obvious that OS can overwrite BIOS's settings. However, there are cases OS should not control ASPM, especially there are bugs in hardware that cause ASPM to fail or systems to hang. BIOS can workaround it by including a blacklist that disables L02 and/or L1 for particular hardware.

How does BIOS tell OS not to control PCIe ASPM? The answer is in the BOOT_ARCH in the ACPI FADT:
===================================
...
Boot Flags (decoded below) : 0002

   Legacy Devices Supported (V2) : 0
   8042 Present on ports 60/64 (V2) : 1
   VGA Not Present (V4) : 0
   MSI Not Supported (V4) : 0
   PCIe ASPM Not Supported (V4) : 0

...

================================

If BIOS needs OS not to control ASPM, it needs to set BOOT_ARCH[4] to 1, and OS should not change any ASPM settings.

However, Linux kernel today will disable all L0s and L1 if PCIe ASPM Controls is set to 1. Matthew Garret submitted a patch to fix it and it should be included in future releases.